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| K6F2008S2E Family Document Title 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM CMOS SRAM Revision History Revision No. History 0.0 1.0 Initial Draft Finalize Draft Date February 28, 2001 Remark Preliminary September 27, 2001 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 1.0 September 2001 K6F2008S2E Family 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM FEATURES * Process Technology: Full CMOS * Organization: 256Kx8 * Power Supply Voltage: 2.3~2.7V * Low Data Retention Voltage: 1.5V(Min) * Three State Outputs * Package Type: 32-TSOP1-0813.4F CMOS SRAM GENERAL DESCRIPTION The K6F2008S2E families are fabricated by SAMSUNGs advanced Full CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed(ns) Standby (ISB1, Typ) 0.5A2) Operating (ICC1, Max) 2mA PKG Type K6F2008S2E-F Industrial(-40~85C) 2.3~2.7V 701)/85ns 32-TSOP1-0813.4F 1. The parameter is measured with 30pF test load. 2. Typical value are measured at VCC=2.5V, TA=25C, and not 100% tested. PIN DESCRIPTION A11 A9 A8 A13 WE CS2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. Address 32-sTSOP Type1-Forward Row select Memory array 1024 rows 256x8 columns I/O1 I/O8 Data cont I/O Circuit Column select Data cont Name Function Name Function Address CS1, CS2 Chip Select Input OE WE Output Enable Write Enable Input I/O1~I/O8 Data Inputs/Outputs Vcc Vss Power Ground CS1 CS2 WE OE Control logic A0~A17 Address Inputs SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 September 2001 K6F2008S2E Family PRODUCT LIST Industrial Temperature Products(-40~85C) Part Name K6F2008S2E-YF70 K6F2008S2E-YF85 Function CMOS SRAM 32-sTSOP1-F, 70ns, 2.5V, LL 32-sTSOP1-F, 85ns, 2.5V, LL FUNCTIONAL DESCRIPTION CS1 H X1) L L L CS2 X 1) OE X 1) WE X 1) I/O High-Z High-Z High-Z Dout Din Mode Deselected Deselected Output Disable Read Write Power Standby Standby Active Active Active L H H H X1) H L X 1) X1) H H L 1. X means dont care (Must be high or low states) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V -0.2 to 3.0 1.0 -65 to 150 -40 to 85 Unit V V W C C 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 1.0 September 2001 K6F2008S2E Family RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 2.3 0 2.0 -0.23) Typ 2.5 0 - CMOS SRAM Max 2.7 0 Vcc+0.2 2) 0.6 Unit V V V V Note: 1. Industrial Product: TA=-40 to 85C, unless otherwise specified. 2. Overshoot: Vcc+1.0V in case of pulse width20ns. 3. Undershoot: -1.0V in case of pulse width20ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(CMOS) VOL VOH ISB1 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH IOL=0.5mA IOH=-0.5mA Other inputs=Vss to Vcc 1) CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or 2) 0VCS20.2V CS2 controlled) VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc Cycle time=1s, 100% duty, IIO=0mA, CS10.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V 85ns 70ns Test Conditions Min -1 -1 2.0 Typ 1) 0.5 Max 1 1 2 12 15 0.4 5 Unit A A mA mA mA V V A 1. Typical value are measured at VCC=2.5V, TA=25C, and not 100% tested. 4 Revision 1.0 September 2001 K6F2008S2E Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.1V Output load (See right): CL=100pF+1TTL CL=30pF+1TTL CMOS SRAM VTM3) R12) CL1) R23) 1. Including scope and jig capacitance 2. R1=3070, R2=3150 3. VTM =2.3V AC CHARACTERISTICS(Vcc=2.3~2.7V, Industrial product: TA=-40 to 85C) Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Read Chip Select to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z 1. The parameter is measured with 30pF test load. 70ns1) Max 70 70 35 25 25 20 Min 85 10 5 0 0 10 85 70 0 70 60 0 0 35 0 5 70 10 5 0 0 10 70 60 0 60 50 0 0 30 0 5 85ns Max 85 85 40 25 25 25 - Units tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS1Vcc-0.2V1) Vcc=1.5V, CS1Vcc-0.2V1) Min 1.5 0 tRC Typ2) 0.5 Max 2.7 2 Unit V A ns See data retention waveform 1. 1) CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or 2) 0CS20.2V(CS2 controlled). 2. Typical value are measured at TA=25C and not 100% tested. 5 Revision 1.0 September 2001 K6F2008S2E Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address tOH Data Out Previous Data Valid tAA (Address Controlled, CS1=OE=VIL, WE=VIH) CMOS SRAM tRC Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE tOH OE tOLZ tLZ Data Valid tOHZ Data out NOTES (READ CYCLE) High-Z 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 1.0 September 2001 K6F2008S2E Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) CMOS SRAM tWC Address tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4) TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4) Data out High-Z High-Z 7 Revision 1.0 September 2001 K6F2008S2E Family TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) tWC Address tAS(3) CS1 tAW CS2 tWP(2) tWP(1) tDW Data in Data Valid tDH tCW(2) tWR(4) CMOS SRAM WE Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2) applied in case a write ends as CS2 going to low. DATA RETENTION WAVE FORM CS1 controlled VCC 2.3V tSDR Data Retention Mode tRDR 2.0V VDR CS1VCC - 0.2V CS1 GND CS2 controlled VCC 2.3V CS2 tSDR Data Retention Mode tRDR VDR 0.4V GND CS20.2V 8 Revision 1.0 September 2001 K6F2008S2E Family PACKAGE DIMENSIONS 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F) CMOS SRAM Units: millimeters(inches) 0.20 0.008 +0.10 -0.05 +0.004 -0.002 13.40 0.20 0.528 0.008 #32 #1 0.10 MAX 0.004 ( 8.40 0.331 MAX 8.00 0.315 0.25 ) 0.010 0.50 0.0197 #16 #17 1.00 0.10 0.039 0.004 0.25 TYP 0.010 11.80 0.10 0.465 0.004 +0.10 -0.05 0.006 +0.004 -0.002 0.15 0.05 0.002 MIN 1.20 0.047 MAX 0~8 0.45~0.75 0.018~0.030 ( 0.50 ) 0.020 9 Revision 1.0 September 2001 |
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